FIG. 1 shows a block diagram of a conventional display module 10. Details of the electrical configuration for driving a simple matrix type liquid crystal panel 16 are illustrated. A plurality of segment electrodes (with N=384, for example) of the liquid crystal panel 16 are driven in parallel by a column driver bank 14 comprising an array of source drivers 14.1-14.x (with x=8, for example), and a plurality of common electrodes are driven by a row driver array 15 while being selected sequentially. An interface is used as the interface between a host computer (not illustrated in FIG. 1) and the display module 10. The interface function 12 is typically realized at the input side of a display timing controller 13. The column driver bank 14 drives, as mentioned, the N columns of the LCD display 16 and it comprises N individual output buffers. Typically, each source driver 14.x of the column driver bank 14 serves n column electrodes of the display panel 16 by providing analog output signals. The row driver array 15 comprises an array of row drivers. Each pixel of the display 16 is a switchable capacitor between a row and a column electrode. The display 16 may be a passive matrix LCD panel, for example.
Display data which represent an image to be displayed on the liquid crystal panel 16 are given to the column driver 14 as serial data by the timing controller 13. Additional signals CLKN, CLKP and LD typically are also supplied to the column driver bank 14 by the controller 13. The controller 13 also supplies signals to the row driver array 15. The row driver array 15 selects a common electrode which should display first in response to a vertical synchronization signal, and thereafter scans in the vertical direction by changing the common electrode to be selected successively while synchronizing with the horizontal synchronization signal.
FIG. 2 shows the internal configuration of the column driver bank 14 shown in FIG. 1. The display data supplied from the controller 13 as serial data IF[1:N] are fed via an input interface 27 and a serial-to-parallel converter 26 for conversion from serial data to parallel data into a data latch 22 according to a data latch clock. A bi-directional shift register 21 is provided in order to be able to switch the direction from which the data are to be displayed on the panel 16. After the data were latched in the data latch 22, they are latched in a line latch 23 at every horizontal scanning period according to a horizontal synchronization signal LD. The data latch 22 serves as “data buffer” for loading data while another data set is read from the line latch 23. The output of the line latch 23 is sent via a digital-to-analog converter 24 to a liquid crystal drive output circuit 25. The data are transferred to the outputs Y1 through Y480 (i.e. N=480 in the present example) by means of the horizontal synchronization signal LD, also referred to as load signal in order to drive the display panel 16. The LD pulse comes in only after a whole line of dots (several source drivers) is ready. The drive output circuit 25 in the present example is able to drive N=480 columns. It comprises N individual output buffers. In FIG. 2, the output buffer of the third column is designated with the reference number 31.
As the FIG. 3 shows, a column of the panel 16 can be regarded as a distributed RC-load. Each of the n rows is represented by an RC network. In FIG. 3 only the third column is depicted. Because in a conventional device the output buffer 31 is biased with a fixed current Ibias, the 1st row settles much earlier than the Mth row, as illustrated by means of two schematic U(t) timing diagrams.
In a conventional source driver 14, the output buffers 31 are designed such that the biasing current Ibias, is defined for the most far away row, that is for the Mth row. As a consequence, those rows that are closer to the output buffer 31 see a biasing current Ibias, that is too high. In other words, theses rows are “overdriven”.
In the U.S. patent application published under US 2003/0112215 A1, a liquid crystal display and driver are described where a timing circuitry is provided that divides each row period into a drive period and a voltage maintenance period. During the driver period the output buffers use a higher biasing current in order to charge the column lines of the display panel. During the maintenance period, a lower biasing current is used to maintain the voltage on the column lines. This solution does, however, not address the problem described above where certain rows are driven with currents that are too high.
Thus, it would be generally desirable to reduce the power required to be drawn by the buffers.
It is thus an object of the present invention to provide a solution that takes into account the distance of the individual rows.
It is a further objective of the present invention to provide a concept for reducing the power consumption of an LCD driver.
It is a further objective of the present invention to improve conventional LCD drivers and to reduce their current consumption.